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Semiconductor
MSM5117800D
2,097,152-Word 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
This version:Apr.1999
DESCRIPTION
The MSM5117800D is a 2,097,152-word 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117800D achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117800D is available in a 28-pin plastic SOJ, 28-pin plastic TSOP.
FEATURES
* * *
* * *
2,097,152-word 8-bit configuration Single 5V power supply, 10% tolerance Input
Output Refresh
: TTL compatible, low input capacitance
: TTL compatible, 3-state : 2048 cycles/32 ms
Fast page mode, read modify write capability
*
* *
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Multi-bit test mode capability Package options:
28-pin 400mil plastic SOJ 28-pin 400mil plastic TSOP
(SOJ28-P-400-1.27) (TSOPII28-P-400-1.27-K) (TSOPII28-P-400-1.27-L)
(Product : MSM5117800D-xxJS) (Product : MSM5117800D-xxTS-K) (Product : MSM5117800D-xxTS-L) xx : indicates speed rank.
PRODUCT FAMILY
Family MSM5117800D-50 MSM5117800D-60 MSM5117800D-70 Access Time (Max.) tRAC 50ns 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 90ns 110ns 130ns Power Dissipation Operating (Max.) 550mW 495mW 440mW 5.5mW Standby (Max.)
1/14
MSM5117800D
PIN CONFIGRATION (TOP VIEW)
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 WE 6 RAS 7 NC 8 A10R 9 A0 10 A1 11 A2 12 A3 13 VCC 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 WE 6 RAS 7 NC 8 A10R 9 A0 10 A1 11 A2 12 A3 13 VCC 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC DQ1 DQ2 DQ3 DQ4 WE RAS NC A10R A0 A1 A2 A3 VCC
28-Pin Plastic SOJ
28-Pin Plastic TSOP (K Type)
28-Pin Plastic TSOP (L Type)
Pin Name A0-A9, A10R RAS CAS DQ1-DQ8 OE WE VCC VSS NC
Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection
2/14
MSM5117800D
BLOCK DIAGRAM
RAS CAS
Timing Generator
WE
I/O Controller
OE
8
Output Buffers
8
DQ1 - DQ8
10 Column Address Buffers Internal Address Counter 10 Column Decoders 8 I/O Selector Input Buffers 8
A0 - A9
Refresh Control Clock
Sense Amplifiers
8
8
10
A10R
1
Row Address Buffers
11
Row Decoders
Word Drivers
Memory Cells
VCC
On Chip VBB Generator On Chip IVCC Generator
VSS
3/14
MSM5117800D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage VCC supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg *: Ta = 25C Rating -0.5 to VCC + 0.5 0.5 to 7.0 50 1 0 to 70 -55 to 150 Unit V V mA W C C
Recommended Operating Conditions
(Ta = 0C to 70C)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 4.5 0 2.4 -0.5
*2
Typ. 5.0 0 3/4 3/4
Max. 5.5 0
Unit V V V V
VCC VSS VIH VIL
VCC + 0.5*1
0.8
Notes:
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied).
Capacitance
(VCC = 5V 10%, Ta = 25C, f=1MHz)
Parameter Input Capacitance (A0 - A9, A10R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ8) Symbol Typ. 3/4 3/4 3/4 Max. 5 7 7 Unit pF pF pF
CIN1 CIN2 CI/O
4/14
MSM5117800D
DC Characteristics
(VCC = 5V 10%, Ta = 0C to 70C)
MSM5117800 MSM5117800 MSM5117800 D-50 D-60 D-70 Unit Min. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) VOH VOL IOH = -5.0mA IOL = 4.2mA 0V VI 6.5V ; ILI All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC - 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. 3/4 80 3/4 70 3/4 60 mA 1,3 3/4 5 3/4 5 3/4 5 mA 1 3/4 100 3/4 90 3/4 80 mA 1,2 -10 10 -10 10 -10 10 mA 2.4 0 Max VCC 0.4 Min. 2.4 0 Max VCC 0.4 Min. 2.4 0 Max VCC 0.4 V V
Parameter
Symbol
Condition
Note
ILO
-10
10
-10
10
-10
10
mA
ICC1
3/4 3/4 3/4
100
3/4 3/4 3/4
90
3/4 3/4 3/4
80
mA
1,2
2 1
2 1
2 1 mA 1
ICC6
3/4
100
3/4
90
3/4
80
mA
1,2
Notes: 1. 2. 3.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH.
5/14
MSM5117800D
AC Characteristic (1/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3,11,12
MSM5117800 D-50 Symbol Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS 90 131 35 76 3/4 3/4 3/4 3/4 3/4 0 0 0 3 3/4 30 50 50 13 13 7 13 50 5 30 17 12 0 7 0 Max. 3/4 3/4 3/4 3/4 50 13 25 30 13 3/4 13 13 50 32 3/4 10,000 100,000 3/4 3/4 3/4 10,000 3/4 3/4 3/4 37 25 3/4 3/4 3/4 MSM5117800 D-60 Min. 110 155 40 85 3/4 3/4 3/4 3/4 3/4 0 0 0 3 3/4 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 Max. 3/4 3/4 3/4 3/4 60 15 30 35 15 3/4 15 15 50 32 3/4 10,000 100,000 3/4 3/4 3/4 10,000 3/4 3/4 3/4 45 30 3/4 3/4 3/4 MSM5117800 D-70 Min. 130 185 45 100 3/4 3/4 3/4 3/4 3/4 0 0 0 3 3/4 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 Max. 3/4 3/4 3/4 3/4 70 20 35 40 20 3/4 20 20 50 32 3/4 10,000 100,000 3/4 3/4 3/4 10,000 3/4 3/4 3/4 50 35 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns ns ns ns m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4,5,6 4,5 4,6 4 4 4 7 7 3
Parameter
Unit
Note
RAS Pulse Width (Fast Page Mode) tRASP RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time tRSH tROH tCP tCAS tCSH tCRP
RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time tRCD tRAD tASR tRAH tASC
6/14
MSM5117800D
AC Characteristic (2/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3,11,12
MSM5117800 D-50 Min. Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH 7 25 0 0 0 0 7 7 13 13 13 0 7 13 36 48 73 53 10 10 10 10 10 10 10 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MSM5117800 D-60 Min. 15 30 0 0 0 0 10 10 15 15 15 0 15 15 40 55 85 60 10 10 10 10 10 10 10 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MSM5117800 D-70 Min. 15 35 0 0 0 0 15 10 20 20 20 0 15 20 50 65 100 70 10 5 10 10 10 10 10 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9
Parameter
Symbol
Unit
Note
7/14
MSM5117800D
Notes:
1.
A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 5ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. tRCH or tRRH must be satisfied for a read cycle. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
2. 3.
4. 5.
6.
7.
8. 9.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheets is a 2-bit parallel test function, CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
8/14
MSM5117800D
Timing Chart
* Read Cycle
tRC tRAS tRP tCRP tCSH tRCD tRAD tRAL tASR tRAH tASC
Column
RAS
VIH VIL
CAS
VIH VIL
tRSH tCAS
tCRP
tCAH
Address
VIH VIL VIH VIL VIH VIL
Row
tRCS tAA tROH tOEA tCAC tRAC
tRRH tRCH
WE
OE
tOEZ tCLZ
Valid Data-out
tOFF
DQ
VOH VOL
Open
"H" or "L" * Write Cycle (Early Write)
RAS
VIH VIL tCRP tRCD tRAD
tRC tRAS tRP tCSH tRSH tCAS tRAL tCRP
CAS
VIH VIL tASR
tRAH
tASC
tCAH
Column
Address
VIH VIL
Row
tCWL tWCS tWP tWCH
WE
VIH VIL VIH VIL VIH VIL
tRWL
OE
tDS
Valid Data-in
tDH
Open
DQ
"H" or "L"
9/14
*
Read Modify Write Cycle
MSM5117800D
tRWC RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC
Column
tRAS tRP tCSH tRCD tRSH tCAS tCWL tRWL tCRP
tCAH
Row
tRCS tRWD
tCWD
tWP
WE
VIH VIL VIH VIL tRAC tCLZ tCAC tOEZ
Valid Data-out
tAWD tAA tOEA tOED tDS
Valid Data-in
tOEH
OE
tDH
DQ
VI/OH VI/OL
"H" or "L"
10/14
MSM5117800D * Fast Page Mode Cycle
tRASP RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC tCAC DQ VOH VOL tCLZ tCPA tOFF tOEZ
Valid Data-out
tRP tPC tRHCP tCP tCAS tRSH tCAS tRAL tASC
Column
tRCD tCAS tRAD tCSH tRAH tASC
tCP
tCRP
tCAH
tASC
tCAH
tCAH
Row
Column
Column
tRCS WE tAA
tRCH tAA tOEA
tRCS
tRCH tAA
tRCS
tRCH
tOEA tCPA tOFF tOEZ
Valid Data-out
tOEA
tRRH
OE
tCAC tCLZ
tCAC tCLZ tOEZ
Valid Data-out
tOFF
"H" or "L"
*
Fast Page Mode Write Cycle (Early Write)
tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL
Row
tRP tPC tRHPC tCP tCAS tRSH tCAS tRAL tCAH
Column
tCRP
tRCD tCAS tRAD tRAH tASC tCSH tCAH
tCP
tCRP
CAS
tASC
tCAH
tASC
Column
Column
tWCS WE VIH VIL tDS DQ VIH VIL
tWCH tWP
tCWL tWCS
tCWL tWCH tWP tDH
Valid * Data-in
tRWL tCWL tWCS tWP tWCH
tDH
Valid * Data-in
tDS
tDS
Valid * Data-in
tDH
Note: OE = "H" or "L"
"H" or "L"
11/14
MSM5117800D * Fast Page Mode Read Modify Write Cycle
tRASP RAS VIH VIL VIH VIL tRAH tASR Address VIH VIL
Row
tCSH tRCD tRAD tASC
C olum n
tPRWC tCAS tCP tCAS tCAH tCAH tCWL tASC tCWL
Column Column
tRSH tCP tCAS tCAH tASC tCRP
tRP
CAS
tRAL
tRCS WE VIH VIL tRAC tAA
tPWD tCWD tAWD tWP tDH tDS tOEA
tRCS
tCPWD
tCWD tAWD tCPA tAA tOEA tOED tOEZ Ou tCLZ In tCLZ tWP tDS tDH tAA
tRCS tCPWD tCWD tAWD tROH tCPA tOEA tOED tOEZ Ou In
tCWL tRWL
tWP tDH tDS
OE
VIH VIL tCAC VI/OH VI/OL tCLZ
tOED tOEZ Out In tCAC
tCAC
DQ
"H" or "L"
*
RAS-only Refresh Cycle
tRC RAS VIH VIL tCRP CAS VIH VIL VIH VIL VOH VOL tASR tRAH tRPC tRAS tRP
Address
Row
tOFF
Open
DQ
Note: WE, OE = "H" or
"H" or "L"
12/14
MSM5117800D * CAS before RAS Refresh Cycle
tRP RAS VIH VIL tRPC tCP tCSR tCHR tOFF DQ VOH VOL tRAS
tRC
tRP tRPC
CAS
VIH VIL
Open
Note: WE, OE, Address = "H" or
"H" or "L"
*
Hidden Refresh Read Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAL tAA tROH OE VIH VIL VOH VOL
Open
tRAS tCRP tRCD tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRP
CAS
tASC
Column
tCAH
tRCS WE
tCAC
tRRH
tOFF
tOEA tRAC tCLZ
Valid Data-out "H" or "L"
tOEZ
DQ
13/14
MSM5117800D Hidden Refresh Write Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL VIH VIL VIH VIL tDS tDH tWP tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRAL tRP
tRAS tCRP tRCD
CAS
tASC
Column
tCAH
tWCS WE
tWCH
OE
DQ
Valid Data-in "H" or "L"
14/14

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